Asynchronous concurrency is becoming ubiquitous, from the micro scale of embedded systems (asynchronous logic, network-on-chip, GALS, multi-core processors, etc.) to the macro scale of grids and cloud computing. In the race for improved performance and lower power consumption, hardware architects are moving towards asynchrony, in which several entities operate concurrently without a central clock. The price to pay for enhanced performance is an increased design complexity, which can only be addressed by formal verification.

To improve the state-of-the-art in the design and analysis of concurrent asynchronous systems, CONVECS follows a research programme of five interrelated scientific topics:

1. From high-level formal languages to concurrent implementations.


2. Parallel and distributed verification algorithms.


3. Handling of timed, probabilistic, and stochastic aspects.


4. Component-based architectures for on-the-fly verification.


5. Real-world applications and case-studies.